Search - FPGA DDS

[VHDL-FPGA-Verilog] prog_dds

Description: FPGA VHDL DDS程序，采用FPGA实现1hz到100khz可调的dds程序，频率调节步长是变化的。-FPGA VHDL DDS program, using FPGA to achieve 1hz to 100khz adjustable dds procedures, the frequency adjustment step size is changing.
Platform: | Size: 1240064 | Author: 张鹏 | Hits:

[VHDL-FPGA-Verilog] tiaopin

Description: 开题报告，基于Quartus ii的DDS设计和实现。-Opening report, based on Quartus ii of DDS design and implementation.
Platform: | Size: 146432 | Author: fangming | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于fpga技术，采用DDS原理产生3MHZ的正弦波。 -Produced with the DDS sine wave 3MHZ.
Platform: | Size: 1024 | Author: 王伟 | Hits:

[assembly language] sin

Description: sin正弦波的产生 DDS FPGA VHDL语言-sin sine wave generation DDS FPGA VHDL language
Platform: | Size: 1731584 | Author: 王盛力 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于FPGA的DDS波形信号发生器，功能强大，代码规范，值得学习-FPGA-based DDS waveform signal generator, powerful, code specifications, it is worth learning
Platform: | Size: 2561024 | Author: Andy Lao | Hits:

[VHDL-FPGA-Verilog] wcy

Description: FPGA-based direct digital synthesizer (DDS) design (source code)
Platform: | Size: 670720 | Author: wangchuanyang | Hits:

[VHDL-FPGA-Verilog] dds

Description: 本设计使用8051单片机ip核，并用VHDL语言设计DDS的各功能模块，利用顶层设计的思想组合成DDS（直接数字频率综合）函数信号发生器，并与单片机ip核的I/O口相连。编译完下载到可编程逻辑器件中（FPGA），实现相应的功能。该设计中使用的是LCD2004液晶显示。-dds
Platform: | Size: 2048 | Author: kelas | Hits:

[SCM] dds

Description: MSP430控制FPGA实现DDS的程序！-FPGA realization of DDS MSP430 control procedures!
Platform: | Size: 41984 | Author: 甘旭东 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 在FPGA中实现频率源的设计,使用硬件描述语言加以实现。-design DDS with verilog language
Platform: | Size: 125952 | Author: lin | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 本代码在fpga中实现了dds，程序有三个按键：一个控制产生的波形（正弦波或方波），另两个控制频率增加或降低。程序附有注释，并在signaltap中仿真成功。-The code is implemented in fpga a dds, program has three buttons: a control generated waveform (sine or square wave), the other two control the frequency increase or decrease. Program with comments, and success in signaltap the simulation.
Platform: | Size: 2167808 | Author: 郝强 | Hits:

[VHDL-FPGA-Verilog] ddsVHDL

Description: fpga设计dds实现调频调相调占空比并用modelsim仿真成功-dds fpga vhdl
Platform: | Size: 6511616 | Author: cc | Hits:

[VHDL-FPGA-Verilog] DDS__FPGA

Description: 基于FPGA的DDS信号发生器设计，包含Quartus 的工程，打开即可使用，Verilog 语言编写！-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读显示对应的拉丁字符的拼音字典- 查看字典详细内容
Platform: | Size: 92160 | Author: 小何 | Hits:

[VHDL-FPGA-Verilog] mcu-fpga

Description: 目录 FPGA & MCU 开发板介绍实验1 QuartusII 软件应用实验2 Keil C51 应用实验3 字符型LCD YM1602 的应用实验4 带字库的中文LCD YM12864 的应用实验5 时钟芯片DS1302 的应用实验6 I2C 总线器件AT24C64 的应用实验7 数字温度传感器的应用实验8 行列式键盘实验9 硬件电子琴的设计实验10 AD 与DA 的使用实验11 简易DDS 信号源设计实验12 用模拟示波器显示多路波形实验13 Quartus Ⅱ 内嵌逻辑分析仪SignalTap Ⅱ的使用附录1 FPGA 驱动程序下载线安装步骤附录2 YM12864 指令表附录3 开发板原理图-Catalog FPGA & MCU Development Board introduced the software application test experiment 1 QuartusII 2 Keil C51 character LCD YM1602 Application Experiment 3 Experiment 4, the application of the Chinese character LCD YM12864 with the application of experimental application of 5 DS1302 clock chip experiment 6 I2C bus devices AT24C64 the Application of experimental application of digital temperature sensor 7 Experiment 8 Experiment 9 determinant hardware keyboard keyboard design experiments 10 AD and the DA' s 11 easy to use experimental design experiments DDS signal source 12 with the analog oscilloscope waveform display multiple experiments embedded logic analyzer 13 Quartus Ⅱ the use of instruments SignalTap Ⅱ Appendix 1 FPGA download cable driver installation steps in Appendix 2 YM12864 instruction sheet Appendix 3 development board schematics
Platform: | Size: 1640448 | Author: lyy | Hits:

[SCM] dfefe.doc

Description: 该高频正弦信号发生器基于直接数字频率合成（DDS）和数字锁相环技术（DPLL），以微控制器（MCU）和现场可编程逻辑门阵列（FPGA）为核心，辅以必要的外围电路设计而成。系统主要由正弦信号发生、红外遥控、高速模数（A/D）－数模（D/A）转换、信号调制和后级处理等模块组成。-The high-frequency sinusoidal signal generator based on Direct Digital Synthesis (DDS) and digital PLL (DPLL), a microcontroller (MCU) and field programmable gate array (FPGA) as the core, supplemented by the necessary peripheral from circuit design. System is composed of sinusoidal signal, infrared remote control, high-speed module (A/D)- digital-analog (D/A) conversion, signal modulation and post-level processing modules.
Platform: | Size: 243712 | Author: henry | Hits:

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[VHDL-FPGA-Verilog] prog_dds

[VHDL-FPGA-Verilog] tiaopin

[VHDL-FPGA-Verilog] DDS

[assembly language] sin

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] wcy

[VHDL-FPGA-Verilog] dds

[SCM] dds

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] ddsVHDL

[VHDL-FPGA-Verilog] DDS__FPGA

[VHDL-FPGA-Verilog] mcu-fpga

[SCM] dfefe.doc

[VHDL-FPGA-Verilog] dds--FPGA

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] dds-design

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] FPGA-DDS

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